1. Field of the Invention
The present invention relates generally to power transistor structure and devices, more particularly, to a power transistor and device having a Schottky or Schottky-like contact.
2. Description of the Prior Art
Voltage regulation is important where circuits are sensitive to transients, noise and other types of disturbances. The device temperature is key to many applications. Additionally, power consumption is also a key design requirement.
Power transistors are used for many applications, such as direct current (DC) to direct current (DC) conversion, voltage regulation, and battery management, in fields such as mobile electronics, consumer electronics, and automotive electronics. These applications are often subject to harsh electrical environments that lead to operating conditions which require the device to withstand high voltages and high currents simultaneously.
The area within the boundary of the operating conditions that avoids electrical overstress (e.g. over-current, over-voltage and over-power) is referred to as the safe operating area (SOA). In the conventional art, large excursions of voltage and current can lead to activation of a parasitic bipolar transistor inherent in many power transistors, leading to destructive failure.
To avoid electrical overstress and potential device failures, the maximum rated operating voltage for a device includes a safety margin substantially less than the physical breakdown voltage of the device. However, this approach increases the on-state resistance of the device which limits the efficiency of the device and wastes electrical power.
Alternative approaches to alleviate the Safe Operating Area (SOA) limitation is achieved by introducing deep p+ regions into the p-body in the device and/or using recessed contact structures. These alternative approaches lead to increased complexity, increased die area, and increased cost.
By way of example the following are relevant prior art documents:
U.S. Pat. No. 6,744,103 B2 for “Short-channel Schottky-barrier MOSFET device and manufacturing method” by inventor John P. Snyder, filed Sep. 6, 2002, describes a MOSFET device and method of fabricating. The MOSFET device utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.
U.S. Publication No. 2010/0059819 for “Power transistor with metal source and method of manufacture” by inventor John P. Snyder, filed Aug. 20, 2009, describes a metal source power transistor device and method of manufacture. The metal source power transistor having a source which is comprised of metal and which forms a Schottky barrier with the body region and channel region of the transistor. The metal source power transistor is unconditionally immune from parasitic bipolar action and, therefore, the effects of snap-back and latch-up, without the need for a body contact. The ability to allow the body to float in the metal source power transistor reduces the process complexity and allows for more compact device layout.
U.S. Pat. No. 8,058,167 B2 for “Dynamic Schottky barrier MOSFET device and method of manufacture” by inventor John P. Snyder, filed Sep. 28, 2009, describes a device for regulating a flow of electric current and its manufacturing method. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.
U.S. Pat. No. 4,983,535A for “Vertical DMOS transistor fabrication process” by inventor Richard A. Blanchard, filed Dec. 28, 1988, describes a process for fabricating a vertical DMOS transistor. The starting material is a heavily doped silicon wafer which has an epitaxial layer thereon. A DMOS body region is diffused into the epitaxial layer and a deep body contact region created. The source is a refractory metal Schottky barrier located on top of the body region. A trench is etched into the epitaxial layer so as to fully penetrate the body region and the trench surfaces oxidized to form a gate oxide. The trench is then filled with doped polysilicon to create a gate electrode. The resulting DMOS has a relatively short channel and the parallel bipolar parasitic transistor cannot be turned on.
U.S. Pat. No. 6,777,745 B2 for “Symmetric trench MOSFET device and method of making same” by inventor Fwu-Iuan Hshieh et al., filed Jun. 14, 2001, descries A trench MOSFET transistor device and method of making the same are provided. The trench MOSFET transistor device comprises: (a) a drain region of first conductivity type; (b) a body region of a second conductivity type provided over the drain region, such that the drain region and the body region form a first junction; (c) a source region of the first conductivity type provided over the body region, such that the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising (i) an insulating layer, which lines at least a portion of the trench and (ii) a conductive region, which is disposed within the trench adjacent the insulating layer. The body region in this device is separated from the source metal. Moreover, the doping profile within the body region and within at least a portion of the source and drain regions, when taken along a line normal to upper and lower surfaces of the device, is such that the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.
U.S. Pat. No. 9,337,329 B2 for “Method of fabrication and device configuration of asymmetrical DMOSFET with schottky barrier source” by inventor Yongzhong Hu et al., filed Sep. 8, 2011, describes a trenched semiconductor power device including a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source and that may include a PtSi, ErSi layer and may further be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer.
U. S. Pat. No. 6,900,101 B2 for “LDMOS transistors and methods for making the same” by inventor John Lin, filed Jun. 13, 2003, describes LDMOS transistor devices and fabrication methods. Additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.
U.S. Pat. No. 6,876,035 B2 for “High voltage N-LDMOS transistors having shallow trench isolation region” by inventors Wagdi W. Abadeer et al., filed May 06, 2003, describes a method and structure for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.
U.S. Pat. No. 7,576,388 B1 for “Trench-gate LDMOS structures” by inventors Peter H. Wilson et al., filed Sep. 26, 2004, describes MOSFET devices for RF applications that use a trench-gate in place of the lateral gate conventionally used in lateral MOSFET devices. A trench-gate provides devices with a single, short channel for high frequency gain. Embodiments of the present invention provide devices with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Refinements to these TG-LDMOS devices include placing a source-shield conductor below the gate and placing two gates in a trench-gate region. These improve device high-frequency performance by decreasing gate-to-drain capacitance. Further refinements include adding a charge balance region to the LDD region and adding source-to-substrate or drain-to-substrate vias. U.S. Pat. No. 7,576,388 describes a structure and method for a trench-gate LDMOS structure as shown in the prior art figures.
U.S. Pat. No. 5,960,271 A for “Short channel self-aligned VMOS field effect transistor” by inventors Donald L. Wollesen et al., filed Mar. 17, 1998, describes a field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls is rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self-aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.
U.S. Pat. No. 5,808,340 A for “Short channel self aligned VMOS field effect transistor” by inventors Donald L. Wollesen et al., filed Sep. 18, 1996, describes A field effect transistor with a trench or groove gate having V-shaped walls is formed in a semiconductor substrate and a gate oxide is grown on the V-shaped walls to the surface of substrate and filled with a gate electrode material, such a polysilicon. Preferably, the bottom of the V-shaped walls is rounded before the trench is filled. Source/drain impurities either are diffused or implanted into the areas of the substrate on both sides of the surface oxide of the V-shaped gate. Contacts are made to the source, drain, and gate within field isolation to complete the structure. The resultant FET structure comprises a self-aligned V-shaped gate having conventional source and drain surrounded by field isolation but with an effective channel length (Leff) of less than about one-half of the surface width of the gate. Preferably, the converging walls of the V-shaped gate end in a rounded concave bottom. Because of the V-shaped structure of the gate, the effective saturated length of the channel with drain voltage applied only extends from the edge of the source to just prior to the tip of the V-shaped structure in the interior of the semiconductor substrate. The drain side of the V-shaped structure becomes a depletion region due to the applied drain voltage. Due to this characteristic of such a structure, the surface width of the gate can be, for example, two or more times the distance of the desired channel length thereby permitting conventional lithography to be used to define the gate lengths much shorter than the lithographic limit.
U.S. Pat. No. 7,745,846 B2 for “LDMOS integrated Schottky diode” by inventors Jacek Korec et al., filed Jan. 15, 2008, describes a semiconductor device including a substrate having a first conductivity type and a semiconductor layer formed over the substrate and having lower and upper surfaces. A laterally diffused metal-oxide-semiconductor (LDMOS) transistor device is formed over the substrate and includes a source region of the first conductivity type and a drain extension region of the first conductivity type formed in the semiconductor layer proximate the upper surface of the semiconductor layer, and a drain contact electrically connecting the drain extension region to the substrate. A Schottky diode is formed over the substrate and includes at least one doped region of the first conductivity type formed in the semiconductor layer proximate to the upper surface, an anode contact forming a Schottky barrier with the at least one doped region, and a cathode contact laterally spaced from the anode contact and electrically connecting at least one doped region to the substrate.
U.S. Pat. No. 7,960,997 B2 for “Cascode current sensor for discrete power semiconductor devices” by inventor Richard K. Williams, filed Aug. 8, 2007, describes A cascode current sensor includes a main MOSFET and a sense MOSFET. The drain terminal of the main MOSFET is connected to a power device whose current is to be monitored, and the source and gate terminals of the main MOSFET are connected to the source and gate terminals, respectively, of the sense MOSFET. The drain voltages of the main and sense MOSFETs are equalized, in one embodiment by using a variable current source and negative feedback. The gate width of the main MOSFET is typically larger than the gate width of the sense MOSFET. Using the size ratio of the gate widths, the current in the main MOSFET is measured by sensing the magnitude of the current in the sense MOSFET. Inserting the relatively large MOSFET in the power circuit minimizes power loss.
U.S. Pat. No. 5,663,584 A for “Schottky barrier MOSFET systems and fabrication thereof” by inventor James D. Welch, filed Dec. 29, 1994, describes (MOS) device systems-utilizing Schottky barrier source and drain to channel region junctions are disclosed. Experimentally derived results which demonstrate operation of fabricated N-channel and P-channel Schottky barrier (MOSFET) devices, and of fabricated single devices with operational characteristics similar to (CMOS) and to a non-latching (SRC) are reported. Use of essentially non-rectifying Schottky barriers in (MOS) structures involving highly doped and the like and intrinsic semiconductor to allow non-rectifying interconnection of, and electrical accessing of device regions is also disclosed. Insulator effected low leakage current device geometries and fabrication procedures therefore are taught. Selective electrical interconnection of drain to drain, source to drain, or source to source, of N-channel and/or P-channel Schottky barrier (MOSFET) devices formed on P-type, N-type and Intrinsic semiconductor allows realization of Schottky Barrier (CMOS), (MOSFET) with (MOSFET) load, balanced differential (MOSFET) device systems and inverting and non-inverting single devices with operating characteristics similar to (CMOS), which devices can be utilized in modulation, as well as in voltage controlled switching and effecting a direction of rectification.
U.S. Pat. No. 8,508,015 B2 for “Schottky-like contact and method of fabrication” by inventors Martin Ward Allen et al., filed May 19, 2008, describes Schottky-like and ohmic contacts comprising metal oxides on zinc oxide substrates and a method of forming such contacts. The metal oxide Schottky-like and ohmic contacts may be formed on zinc oxide substrates using various deposition and lift-off photolithographic techniques. The barrier heights of the metal oxide Schottky-like contacts are significantly higher than those for plain metals and their ideality factors are very close to the image force controlled limit. The contacts may have application in diodes, power electronics, FET transistors and related structures, and in various optoelectronic devices, such as UV photodetectors.
U.S. Pat. No. 7,081,655 B2 for “Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect” by inventor Witold P. Maszara, filed Dec. 3, 2003, describes a method of forming an abrupt junction device with a semiconductor substrate. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.
U.S. Pat. No. 7,306,998 B2 for “Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect” by inventor Witold P. Maszara, filed Jun. 7, 2005, describes a method of forming an abrupt junction device with a semiconductor substrate. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.
U.S. Pat. No. 8,889,537 B2 for “Implantless dopant segregation for silicide contacts” by inventors Cryil Cabral Jr. et al., filed Jul. 09, 2010, describes a method for formation of a segregated interfacial dopant layer at a junction between a semiconductor material and a silicide layer. the method includes depositing a doped metal layer over the semiconductor material; annealing the doped metal layer and the semiconductor material, wherein the anneal causes a portion of the doped metal layer and a portion of the semiconductor material to react to form the silicide layer on the semiconductor material, and wherein the anneal further causes the segregated interfacial dopant layer to form between the semiconductor material and the silicide layer, the segregated interfacial dopant layer comprising dopants from the doped metal layer; and removing an unreacted portion of the doped metal layer from the silicide layer.
U.S. Pat. No. 4,692,348 A for “Low temperature shallow doping technique” by inventors Gary W. Rubloff et al., filed Jul. 28, 1986, describes a technique for producing very shallow doped regions in a substrate, at low temperatures. The doped regions are not in excess of about 300 angstroms in depth, and are formed at temperatures less than 700° C. These shallow doped regions can be used in different applications, including the fabrication of semiconductor switching devices, diodes, and contacts. Overlayers containing the desired dopants are deposited on the substrate, after which an annealing step is carried out to institute the formation of a metallic compound. When the compound is formed, materials in the overlayers to be used as substrate dopants will be pushed ahead of the interface of the growing compound, and will be snowplowed into the top surface of the substrate, to produce the shallow doped region therein.
U.S. Pat. No. 4,362,597 for “Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices” by inventors Devid B. Fraser et al, filed Jan. 19, 1981, describes a method for fabricating high-conductivity silicide-on-polysilicon for MOS devices. It is known to deposit a refractory metal silicide on a polysilicon gate layer to form a low-resistivity composite structure. For VLSI MOS devices, very-high-resolution patterning of the composite structure is required. In accordance with this invention, a silicide pattern is formed on polysilicon by a lift-off technique. In turn, the patterned silicide is utilized as a mask for anisotropic etching of the underlying polysilicon. High-conductivity composite silicide-on-polysilicon gate structures for VLSI MOS devices are thereby achieved.
None of the prior art documents describes power transistor structures and methods for having a Schottky or Schottky-like contact as the source and/or drain region as provided in the present invention.